In the metallization of high aspect ratio (HAR) via holes and trenches on semiconductor wafers, it is required that the barrier layer and the seed layer have good sidewall and bottom coverage. The barrier layer needs to be as thin as possible without sacrificing its barrier properties. The barrier layer must be thin because its electrical resistance, which adds to the electrical resistance of the via structure, must be minimized. It needs to be conformal and continuous to prevent diffusion of seed layer material into the dielectric layer and into other layers to prevent reliability problems. This requires that the barrier layer thickness must be well controlled and minimized especially at the bottom of the via. A thick barrier layer at the bottom of the via may add substantial undesirable electrical resistance to the resistance of interconnect metallization. High contact resistance results in inferior IC performance. During barrier layer deposition, at the top edges of the via's entrance, an overhang may form due to buildup of thicker material there. This overhang interferes with the deposition of the seed layer onto the sidewalls and the bottom of the via. During seed layer deposition, further overhang formation by the seed layer material itself must be prevented.
The seed layer must be continuous and have good coverage at the sidewalls and at the bottom of the vias. This is essential for the electroplating step which follows the barrier and seed layer deposition. The closure of the via entrance by overhang results in poor sidewall coverage, poor electroplated fill and low device yields.
Ionized PVD has been utilized in semiconductor processing for metallization and interconnects where it promises to extend performance to 65 nanometer or lower submicron technology. In the metallization of high aspect ratio (HAR) via holes and trenches on semiconductor wafers, the barrier layer and the seed layer must have good sidewall and bottom coverage across the wafer. Ionized PVD deposition is used for barrier and seed layer metallization in advanced IC wafers. Ionized PVD provides good sidewall and bottom coverage in via and trench structures. However, the ionized deposition requirements become more critical as the geometries shrink and as the via dimensions decrease below 0.15 micrometers. Therefore, it is highly desirable to have a processing system where bottom and sidewall coverage are well balanced and overhang is minimized.
Sequential deposition and etch processes have been proposed previously. In U.S. Pat. No. 6,100,200, Van Buskirk, et al. teach a sequentially performed heated deposition and etch unit process to provide conformal coverage of via or trench structures. However, they teach deposition and etch processes at high substrate temperatures between 300-600° C. Unfortunately, the new state-of-the-art low-k dielectrics that are used in current semiconductor processes require temperatures<200° C. Cu seed layer deposition requires <0° C., typically −20° C. to −50° C. to prevent copper agglomeration. The temperatures taught by Van Buskirk, et al. would result in total agglomeration of Cu seed layers, overhang and closure of via and trenches with large islands of Cu and discontinuous Cu layers. Van Buskirk, et al. also teaches low power sputtering typically less than 1 kW and particularly less than 0.5 kW. This puts severe deposition rate and throughput limitations on the process.
Furthermore, Van Buskirk, et al. teach sequential deposition and etching steps to be carried out in a singular vacuum system by transporting the wafer between dedicated deposition and etch modules, or in a singular vacuum system using a multi-faceted deposition and reactive ion etch module. Alternatively, Van Buskirk et al. suggests the steps may be carried out in independent deposition and etch systems. Transferring the wafer from one etch chamber to another deposition chamber or from an etch station to another deposition station within the same module has disadvantages both from cost of process and quality of process points of view. By transferring wafers from chamber to chamber or from one station to another station in the same chamber, loss of throughput results, and thus a more costly process. Some processes are sensitive to adsorption of gas molecules or other contaminants during transfer, which may be detrimental to the quality and reliability of the devices under construction. Another suggestion of Van Buskirk, et al. is to carry out the deposition and etch steps in independent systems with exposure to atmosphere in between processes, is totally unacceptable in most of the modern barrier/seed layer metallization processes. Van Buskirk, et al. also do not teach any substrate bias during the deposition step.
In U.S. Pat. No. 4,999,096, Nikei, et al. teach a method of and apparatus for sputtering when sequential deposition and etching in the same chamber can be performed. Nikei, et al. applies a negative voltage alternatively to a target and a substrate to perform film deposition and reverse sputter alternately. They teach an RF coil internal to the process module, situated between the target and substrate, to cause plasma generation for the etch step. This configuration has a significant disadvantage in that the internal coil is a source of contamination because it is well known in the art that energetic ions and neutrals that exist in the process space will also remove material from, i.e., etch, the coils and contaminate the film being deposited or etched on the substrate. In other prior art, the coil can be made from the same material that is being deposited, but this creates undue economic and hardware difficulties for the process. Not every material to be deposited is amenable to construct a coil and most of the time the cost is prohibitive. Furthermore, the suggestions of Nikei, et al. will result in non-uniform plasma generation and non-uniform etching of the substrate. It is essential in a sequential etching and deposition process that both steps be uniform across the wafer to result in a uniformly processed wafer at the end of the process.
Nikei, et al. strictly teach and emphasize a low pressure deposition and etching process to prevent impurity inclusion in the deposited films. This is achieved by creating the plasma at low pressure, such as on the order of 10−3 torr or less during the etch and deposition process. During the etch process the internal coil needs to be RF powered to achieve a discharge which, contrary to their desire to keep certain contaminants from the substrate, now contributes contaminants to the substrate. Nikei, et al. strictly teach or limit their invention to low pressure (10−3 torr or less) operation.
U.S. Pat. No. 6,274,008, Gopalraja, et al. teaches an integrated copper fill process where a simultaneous clean-deposit step is carried out. This invention uses copper ions to clean and/or etch the bottom of via structures before the copper seed layer is deposited.
Furthermore, performing deposition and etching in the same chamber, as proposed by Nikei, et al. and generally, subject one or both of the deposition or etch processes to conditions that, while suitable for the other process, are detrimental. For example, magnetic fields that are important to achieving high deposition as well as target utilization and erosion uniformity during the deposition process can adversely affect the efficiency or uniformity of an etch process performed in a chamber equipped with magnets selected to optimize the deposition.